Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a fine pattern using a double lithography.
As the design rule of a semiconductor device shrinks, the sizes of patterns constituting the semiconductor device have been reduced. As patterns for a dynamic random access memory (DRAM) or a phase change random access memory (PCRAM) become finer, pattern forming techniques using a double lithography or a double patterning have been attempted to fabricate fine patterns on a wafer smaller than a resolution that can be realized in a lithography process.
A first resist pattern is formed and then a second resist pattern is formed on a resulting structure in which the first resist pattern is formed. A fine pattern may be realized by the combination of the first resist pattern and the second resist pattern. However, in the case of coating a resist layer twice and separately performing an exposure process and a development process on the respective resist layers, a process of freezing the first resist pattern is required because the first resist pattern exposed and developed may be influenced and deformed during the subsequent coating, exposure, and development of the second resist layer. As such, since the two-time exposure and development processes, in addition to the freezing process, are required, the process may become quite complicated. Thus, there is a need to develop a method which can further simplify the process of fabricating a fine pattern.